The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components, such as integrated circuit dies, also require smaller packages that utilize less area than packages of the past, in some applications.
Integrated Fan Out (InFO) package technology is becoming increasingly popular, particularly when combined with Wafer Level Packaging (WLP) technology in which integrated circuits are packaged in packages that typically include a redistribution layer (RDL) or post passivation interconnect (PPI) that is used to fan-out wiring for contact pads of the package, so that electrical contacts can be made on a larger pitch than contact pads of the integrated circuit. Such resulting package structures provide for high functional density with relatively low cost and high performance packages.
These packages may be combined in a package-on-package process, wherein a top package is bonded to a bottom package. The top package and the bottom package may also have device dies packaged therein. By adopting the package-on-package (PoP) process, the integration level of the packages is increased.